Increasing operating speeds and computing power of microelectronic devices have led to semiconductor structures having increasing complexity and functionality. Hetero-integration of dissimilar semiconductor materials, for example, III-V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium (Ge) with a silicon (Si) or silicon-germanium (SiGe) substrate, is an attractive path for future fabrication. One technique for such integration is often referred to as “heteroepitaxial growth” or “heteroepitaxy,” epitaxial growth of a semiconductor material over a semiconductor substrate, for example, by chemical vapor deposition (“CVD”) or molecular beam epitaxy (“MBE”), where the semiconductor material, when fully relaxed, has a different lattice constant than the underlying substrate. In particular, heteroepitaxial growth can be advantageously employed to: (i) fabricate semiconductor devices for which lattice-matched substrates are not commercially available, e.g., some types of ultra-high speed radio-frequency (RF) or optoelectronic devices; (ii) combine multiple new materials on a single wafer, e.g., Ge for p-channel field-effect transistor (FET) devices and indium gallium arsenide (InGaAs) or indium antimonide (InSb) for n-channel FET devices; (iii) improve performance of the conventional complementary metal-oxide-semiconductor (CMOS) platform by replacing Si, in active areas of some or all transistors on a wafer, with semiconductor materials with higher mobility and saturation velocity than Si, i.e., Ge and/or III-V materials; and (iv) achieve monolithic integration of semiconductor materials with large mismatch to Si with silicon microelectronics in a manner that is minimally, if at all, disruptive to the CMOS process.
Depending on the application, key considerations for using selective heteroepitaxy for fabrication of semiconductor devices include: control of defect density, surface morphology, and degree of relaxation of the desired portions of heteroepitaxial regions; ease of integration of heteroepitaxy into device manufacturing process; and reliability of electrical isolation of the defective regions from the active regions of the heterostructure.
Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials depend on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties, which, in turn, results in poor material quality and limited performance. In addition, dislocation defects can degrade physical properties of the device material and can lead to premature device failure.
As mentioned above, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material (often referred to as “heterostructure”) due to different crystalline lattice sizes of the two materials. This lattice-mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure. Misfit dislocations form at the mismatched interface to relieve the misfit strain. Many misfit dislocations have vertical components, termed “threading segments,” which terminate at the surface. These threading segments continue through all semiconductor layers subsequently added to the heterostructure. In addition, dislocation defects can arise in the epitaxial growth of the same material as the underlying substrate where the substrate itself contains dislocations. Some of the dislocations replicate as threading dislocations in the epitaxially grown material. Such dislocations in the active regions of semiconductor devices such as diodes, lasers and transistors, may significantly degrade performance.
To reduce formation of dislocations and associated performance issues, many semiconductor heterostructure devices known in the art have been limited to semiconductor layers that have very closely (e.g., within 0.1%) lattice-matched crystal structures. In such devices, a thin layer is epitaxially grown on a mildly lattice-mismatched substrate. As long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer, which elastically conforms to the substrate template. While lattice-matching (or near matching) eliminates dislocations in a number of structures, there are relatively few known lattice-matched systems, limiting the design options for new devices.
Thus, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures that constrain substrate interface defects in a variety of lattice-mismatched materials systems. There is also a need in the art for semiconductor devices utilizing a combination of integrated lattice-mismatched materials with reduced levels of substrate interface defects for improved functionality and performance. There is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than known approaches may allow.
For example, high-quality germanium (Ge) grown epitaxially on silicon (Si) continues to be of interest for many notable applications. Specifically, Ge on Si can be used as a substrate for fabrication of multijunction solar cells (e.g., high-efficiency photovoltaics), high-mobility transistors integrated on Si substrates (e.g., strained Si CMOS technology), and near infrared photodetectors, among other devices. However, difficulties exist in achieving high-quality Ge on Si, as there is a 4.2% lattice-mismatch and 116% thermal expansion coefficient (TEC) mismatch between Ge and Si. The lattice-mismatch can result in relatively high threading dislocation densities (TDDs) on the order of 108-109 cm−2 and the TEC mismatch can lead to microcracks in Ge films or their delamination as the Ge film thickness exceeds several micrometers and the material cools from a growth temperature to room temperature. Further, threading dislocations (TDs) in heteroepitaxial films often propagate to the film surface.
Conventional attempts to reduce the defect density in Ge on Si include using graded GexSi1-x buffer layers, thermal annealing, selective epitaxial overgrowth (SEG), strained-layer deflection, and aspect ratio trapping (ART). These methods have had varying degrees of success. Disadvantages associated with such methods include the need to use thick buffer layers, high temperature processing, and limited area growth.
The ART technique utilizes high-aspect-ratio holes or trenches etched through dielectric films to trap dislocations, reducing dislocation density. ART techniques can avoid the need for thick buffers and high thermal budgets that are typical of other heteroepitaxial techniques. However, the ART technique may not be effective with holes or strips with dimensions greater than 1 μm.
Thus, there is a need to provide heteroepitaxial films on lattice-mismatched substrates (such as, Ge films on Si substrates, among others) and methods for reducing defects when forming semiconductor layers/devices.